Sciweavers

643 search results - page 59 / 129
» Using Hardware Counters to Automatically Improve Memory Perf...
Sort
View
ASPLOS
2010
ACM
14 years 3 months ago
Speculative parallelization using software multi-threaded transactions
With the right techniques, multicore architectures may be able to continue the exponential performance trend that elevated the performance of applications of all types for decades...
Arun Raman, Hanjun Kim, Thomas R. Mason, Thomas B....
MICRO
2009
IEEE
144views Hardware» more  MICRO 2009»
14 years 3 months ago
Characterizing flash memory: anomalies, observations, and applications
Despite flash memory’s promise, it suffers from many idiosyncrasies such as limited durability, data integrity problems, and asymmetry in operation granularity. As architects, ...
Laura M. Grupp, Adrian M. Caulfield, Joel Coburn, ...
ASPLOS
1998
ACM
14 years 29 days ago
Data Speculation Support for a Chip Multiprocessor
Thread-level speculation is a technique that enables parallel execution of sequential applications on a multiprocessor. This paper describes the complete implementation of the sup...
Lance Hammond, Mark Willey, Kunle Olukotun
ASPLOS
2010
ACM
14 years 3 months ago
COMPASS: a programmable data prefetcher using idle GPU shaders
A traditional fixed-function graphics accelerator has evolved into a programmable general-purpose graphics processing unit over the last few years. These powerful computing cores...
Dong Hyuk Woo, Hsien-Hsin S. Lee
ICCD
2005
IEEE
165views Hardware» more  ICCD 2005»
14 years 5 months ago
Applying Resource Sharing Algorithms to ADL-driven Automatic ASIP Implementation
Presently, Architecture Description Languages (ADLs) are widely used to raise the abstraction level of the design space exploration of Application Specific Instruction-set Proces...
Ernst Martin Witte, Anupam Chattopadhyay, Oliver S...