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DATE
2007
IEEE
134views Hardware» more  DATE 2007»
14 years 3 months ago
Non-fractional parallelism in LDPC decoder implementations
Because of its excellent bit-error-rate performance, the Low-Density Parity-Check (LDPC) decoding algorithm is gaining increased attention in communication standards and literatur...
John Dielissen, Andries Hekstra
VLSID
2001
IEEE
164views VLSI» more  VLSID 2001»
14 years 9 months ago
An Efficient Parallel Transparent Bist Method For Multiple Embedded Memory Buffers
In this paper, we propose a new transparent built-in self-test ( TBIST ) method to test multiple embedded memory arrays with various sizes in parallel. First, a new transparent tes...
Der-Cheng Huang, Wen-Ben Jone, Sunil R. Das
ISCA
2003
IEEE
101views Hardware» more  ISCA 2003»
14 years 2 months ago
Overcoming the Limitations of Conventional Vector Processors
Despite their superior performance for multimedia applications, vector processors have three limitations that hinder their widespread acceptance. First, the complexity and size of...
Christoforos E. Kozyrakis, David A. Patterson
DATE
2008
IEEE
114views Hardware» more  DATE 2008»
14 years 3 months ago
Hiding Cache Miss Penalty Using Priority-based Execution for Embedded Processors
—The contribution of memory latency to execution time continues to increase, and latency hiding mechanisms become ever more important for efficient processor design. While high-...
Sanghyun Park, Aviral Shrivastava, Yunheung Paek
CARDIS
2006
Springer
114views Hardware» more  CARDIS 2006»
14 years 15 days ago
A Low-Footprint Java-to-Native Compilation Scheme Using Formal Methods
Ahead-of-Time and Just-in-Time compilation are common ways to improve runtime performances of restrained systems like Java Card by turning critical Java methods into native code. H...
Alexandre Courbot, Mariela Pavlova, Gilles Grimaud...