111 search results - page 13 / 23 » Using Multiple Memory Access Instructions for Reducing Code ... |
APCSAC
2003
IEEE
13 years 11 months ago
2003
IEEE
Very Long Instruction Word (VLIW) architectures exploit instruction level parallelism (ILP) with the help of the compiler to achieve higher instruction throughput with minimal hard...
ICCD
2005
IEEE
14 years 4 months ago
2005
IEEE
Cache memories are commonly implemented through multiple memory banks to improve bandwidth and latency. The early knowledge of the data cache bank that an instruction will access ...
CODES
2002
IEEE
14 years 21 days ago
2002
IEEE
Limited energy and memory resources are important constraints in the design of an embedded system. Compression is an useful and widely employed mechanism to reduce the memory requ...
GLVLSI
2009
IEEE
14 years 2 months ago
2009
IEEE
Implementing a custom hardware is not always feasible due to cost and time considerations. No instruction set computer (NISC) architecture is one of the promising direction to des...
CC
2006
Springer
13 years 11 months ago
2006
Springer
Abstract. Profiling can effectively analyze program behavior and provide critical information for feedback-directed or dynamic optimizations. Based on memory profiling, reuse dista...