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DAC
2006
ACM
16 years 3 months ago
Simultaneous time slack budgeting and retiming for dual-Vdd FPGA power reduction
Field programmable dual-Vdd interconnects are effective to reduce FPGA power. Assuming uniform length interconnects, existing work has developed time slack budgeting to minimize p...
Yu Hu, Yan Lin, Lei He, Tim Tuan
ASPDAC
2006
ACM
148views Hardware» more  ASPDAC 2006»
15 years 6 months ago
TAPHS: thermal-aware unified physical-level and high-level synthesis
Thermal effects are becoming increasingly important during integrated circuit design. Thermal characteristics influence reliability, power consumption, cooling costs, and performan...
Zhenyu (Peter) Gu, Yonghong Yang, Jia Wang, Robert...
125
Voted
AUIC
2005
IEEE
15 years 8 months ago
Real-time 3D Finger Pointing for an Augmented Desk
The augmented desk is gaining popularity in recent HCI research. Its layout of a large horizontal screen on the desk enhances immersive and intense collaborative experiences. A re...
Le Song, Masahiro Takatsuka
CODES
2005
IEEE
15 years 8 months ago
High-level synthesis for large bit-width multipliers on FPGAs: a case study
In this paper, we present the analysis, design and implementation of an estimator to realize large bit width unsigned integer multiplier units. Larger multiplier units are require...
Gang Quan, James P. Davis, Siddhaveerasharan Devar...
126
Voted
ICML
2004
IEEE
16 years 3 months ago
Generative modeling for continuous non-linearly embedded visual inference
Many difficult visual perception problems, like 3D human motion estimation, can be formulated in terms of inference using complex generative models, defined over high-dimensional ...
Cristian Sminchisescu, Allan D. Jepson