610 search results - page 32 / 122 » Using SAT in QBF |
GLVLSI
2009
IEEE
13 years 11 months ago
2009
IEEE
Design debug remains one of the major bottlenecks in the VLSI design cycle today. Existing automated solutions strive to aid engineers in reducing the debug effort by identifying ...
ICES
2003
Springer
14 years 28 days ago
2003
Springer
Abstract. We present a systematic procedure for the synthesis and minimisation of digital circuits using propositional satisfiability. We encode the truth table into a canonical s...
ASE
2004
13 years 7 months ago
2004
TestEra is a framework for automated specification-based testing of Java programs. TestEra requires as input a Java method (in sourcecode or bytecode), a formal specification of th...
CAV
2008
Springer
13 years 9 months ago
2008
Springer
This paper proposes a new approach for deriving invariants that are systems of congruence equations where the modulo is a power of 2. The technique is an amalgam of SAT-solving, wh...
ESSLLI
2009
Springer
13 years 5 months ago
2009
Springer
The polynomial path order (POP for short) is a termination method that induces polynomial bounds on the innermost runtime complexity of term rewrite systems (TRSs for short). Seman...