189 search results - page 7 / 38 » Using constraint logic programming in memory synthesis for g... |
DAC
2006
ACM
14 years 9 months ago
2006
ACM
Highly regular, nanodevice based architectures have been proposed to replace pure CMOS based architectures in the emerging post CMOS era. Since bottom-up self-assembly is used to ...
DAC
2012
ACM
11 years 11 months ago
2012
ACM
In this work we address the problem of managing interconnect timing in high-level synthesis by generating a layoutfriendly microarchitecture. A metric called spreading score is pr...
DAC
2007
ACM
14 years 9 months ago
2007
ACM
Mapping packet processing applications onto embedded network processors (NP) is a challenging task due to the unique constraints of NP systems and the characteristics of network a...
CODES
2005
IEEE
14 years 2 months ago
2005
IEEE
Scripting is a powerful, high-level, cross-platform, dynamic, easy way of composing software modules as black boxes. Unfortunately, the high runtime overhead has prevented scripti...
ICCAD
2009
IEEE
13 years 6 months ago
2009
IEEE
In a behavioral synthesis system, a typical approach used to guide the scheduler is to impose hard constraints on the relative timing between operations considering performance, a...