102 search results - page 9 / 21 » Using embedded FPGAs for SoC yield improvement |
NOCS
2008
IEEE
14 years 1 months ago
2008
IEEE
In this paper we examine a latency insensitive network composed of very fast and simple circuits that connects SoC cores that are also latency insensitive, de-synchronized, or asy...
ASPDAC
2000
ACM
13 years 11 months ago
2000
ACM
- This paper introduces the first hardwarekoftware co-synthesis algorithm that optimizes the implementations of ASICs that are used as processing elements for the embedded systems....
CODES
2007
IEEE
14 years 1 months ago
2007
IEEE
Early embedded SW development with transaction-level models has been broadly promoted to improve SoC design productivity. But the proposed APIs only provide low-level read/write o...
VTS
2006
IEEE
14 years 1 months ago
2006
IEEE
We tackle the problem of fault-free assumptions in current PLB and interconnect built-in-self-test (BIST) techniques for FPGAs. These assumptions were made in order to develop stro...
DDECS
2007
IEEE
14 years 1 months ago
2007
IEEE
: As scan compression replaces the traditional scan it is important to understand how it works with power. DFT MAX represents one of the two primary scan compression solutions used...