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ISLPED
2000
ACM
91views Hardware» more  ISLPED 2000»
14 years 1 months ago
New clock-gating techniques for low-power flip-flops
Two novel low power flip-flops are presented in the paper. Proposed flip-flops use new gating techniques that reduce power dissipation deactivating the clock signal. Presented cir...
Antonio G. M. Strollo, E. Napoli, Davide De Caro
DAC
1999
ACM
14 years 1 months ago
Verification and Management of a Multimillion-Gate Embedded Core Design
Verification is one of the most critical and time-consuming tasks in today's design processes. This paper demonstrates the verification process of a 8.8 million gate design u...
Johann Notbauer, Thomas W. Albrecht, Georg Niedris...
ISER
1999
Springer
114views Robotics» more  ISER 1999»
14 years 1 months ago
Continuous Probabilistic Mapping by Autonomous Robots
In this paper, we present a new approach for continuous probabilistic mapping. The objective is to build metric maps of unknown environments through cooperation between multiple au...
Jesús Salido Tercero, Christiaan J. J. Pare...
ISCA
1998
IEEE
125views Hardware» more  ISCA 1998»
14 years 1 months ago
Active Pages: A Computation Model for Intelligent Memory
Microprocessors and memory systems su er from a growing gap in performance. We introduce Active Pages, a computation model which addresses this gap by shifting data-intensive comp...
Mark Oskin, Frederic T. Chong, Timothy Sherwood
PDP
1997
IEEE
14 years 1 months ago
The controlled logical clock--a global time for trace-based software monitoring of parallel applications in workstation clusters
Event tracing and monitoring of parallel applications are difficult if each processor has its own unsynchronized clock. A survey is given on several strategies to generate a glob...
Rolf Rabenseifner