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» Using the DEVS Paradigm to Implement a Simulated Processor
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DAC
1996
ACM
14 years 26 days ago
Symphony: A Simulation Backplane for Parallel Mixed-Mode Co-Simulation of VLSI Systems
In this paper we present an integrated simulation paradigm in which parallel mixed-mode co-simulation is accomplished by integrating sequential simulators in a software simulation ...
Antonio R. W. Todesco, Teresa H. Y. Meng
EXPCS
2007
14 years 18 days ago
Empirical performance assessment using soft-core processors on reconfigurable hardware
Simulation has been the de facto standard method for performance evaluation of newly proposed ideas in computer architecture for many years. While simulation allows for theoretica...
Richard Hough, Praveen Krishnamurthy, Roger D. Cha...
SAMOS
2010
Springer
13 years 7 months ago
Cycle-accurate performance modelling in an ultra-fast just-in-time dynamic binary translation instruction set simulator
—Instruction set simulators (ISS) are vital tools for compiler and processor architecture design space exploration and verification. State-of-the-art simulators using just-in-ti...
Igor Böhm, Björn Franke, Nigel P. Topham
TON
2010
176views more  TON 2010»
13 years 3 months ago
Approximation of Generalized Processor Sharing With Interleaved Stratified Timer Wheels
This paper presents Interleaved Stratified Timer Wheels as a novel priority queue data structure for traffic shaping and scheduling in packet-switched networks. The data structure ...
Martin Karsten
ISCA
2000
IEEE
103views Hardware» more  ISCA 2000»
14 years 1 months ago
Circuits for wide-window superscalar processors
Our program benchmarks and simulations of novel circuits indicate that large-window processors are feasible. Using our redesigned superscalar components, a large-window processor ...
Dana S. Henry, Bradley C. Kuszmaul, Gabriel H. Loh...