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GLVLSI
1998
IEEE
122views VLSI» more  GLVLSI 1998»
13 years 11 months ago
Reducing Power Consumption of Dedicated Processors Through Instruction Set Encoding
With the increased clock frequency of modern, high-performance processors over 500 MHz, in some cases, limiting the power dissipation has become the most stringent design target. ...
Luca Benini, Giovanni De Micheli, Alberto Macii, E...
VLSID
2002
IEEE
142views VLSI» more  VLSID 2002»
14 years 7 months ago
Degree-of-Freedom Analysis for Sequential Machines Targeting BIST Quality and Gate Area
| This paper reports the design of BIST structures for sequential machines. Testability of an FSM is limited due to the fact that some machine states remain unreachable and some ac...
Samir Roy, Biplab K. Sikdar, Monalisa Mukherjee, D...
FCCM
2000
IEEE
105views VLSI» more  FCCM 2000»
13 years 12 months ago
Configuration Relocation and Defragmentation for Reconfigurable Computing
Custom computing systems exhibit significant speedups over traditional microprocessors by mapping compute-intensive sections of a program to reconfigurable logic [Hauck98]. Howeve...
Katherine Compton, James Cooley, Stephen Knol, Sco...
DAC
2006
ACM
14 years 1 months ago
The zen of nonvolatile memories
Silicon technology based nonvolatile memories (NVM) have achieved widespread adoption for code and data storage applications. In the last 30 years, the traditional floating gate ...
Erwin J. Prinz
CODES
2004
IEEE
13 years 11 months ago
A loop accelerator for low power embedded VLIW processors
The high transistor density afforded by modern VLSI processes have enabled the design of embedded processors that use clustered execution units to deliver high levels of performan...
Binu K. Mathew, Al Davis