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» Validating High-Level Synthesis

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GLVLSI
2000
IEEE

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A new technique for estimating lower bounds on latency for high level synthesis

14 years 3 months ago

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In this paper we present a novel and fast estimation technique that produces tight latency lower bounds for Data Flow Graphs representing time critical segments of the application...

Helvio P. Peixoto, Margarida F. Jacome

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ICCAD
2000
IEEE

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DAISY: A Simulation-Based High-Level Synthesis Tool for Delta-Sigma Modulators

14 years 3 months ago

Download www.cs.york.ac.uk

Kenneth Francken, Peter J. Vancorenland, Georges G...

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VTS
1999
IEEE

106views Hardware» more VTS 1999»

RT-level TPG Exploiting High-Level Synthesis Information

14 years 3 months ago

Download www.cad.polito.it

High-level test pattern generation is today a widely investigated research topic. The present paper proposes a fully automated, simulation-based ATPG system, to address test patte...

Silvia Chiusano, Fulvio Corno, Paolo Prinetto

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ISSS
1996
IEEE

73views Hardware» more ISSS 1996»

Layout-Driven RTL Binding Techniques for High-Level Synthesis

14 years 3 months ago