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» Validating High-Level Synthesis
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GLVLSI
2003
IEEE
134views VLSI» more  GLVLSI 2003»
14 years 4 months ago
Modeling QCA for area minimization in logic synthesis
Concerned by the wall that Moore’s Law is expected to hit in the next decade, the integrated circuit community is turning to emerging nanotechnologies for continued device impro...
Nadine Gergel, Shana Craft, John Lach
ICCAD
2000
IEEE
119views Hardware» more  ICCAD 2000»
14 years 3 months ago
Synthesis of Operation-Centric Hardware Descriptions
Most hardware description frameworks, whether schematic or textual, use cooperating finite state machines (CFSM) as the underlying abstraction. In the CFSM framework, a designer ...
James C. Hoe, Arvind
CODES
2005
IEEE
14 years 4 months ago
High-level synthesis for large bit-width multipliers on FPGAs: a case study
In this paper, we present the analysis, design and implementation of an estimator to realize large bit width unsigned integer multiplier units. Larger multiplier units are require...
Gang Quan, James P. Davis, Siddhaveerasharan Devar...
ICANN
2005
Springer
14 years 4 months ago
Robust Structural Modeling and Outlier Detection with GMDH-Type Polynomial Neural Networks
Abstract. The paper presents a new version of a GMDH type algorithm able to perform an automatic model structure synthesis, robust model parameter estimation and model validation i...
Tatyana I. Aksenova, Vladimir Volkovich, Alessandr...
EUROMICRO
2000
IEEE
14 years 3 months ago
Task Assignment and Scheduling under Memory Constraints
Many DSP and image processing embedded systems have hard memory constraints which makes it difficult to find a good task assignment and scheduling which fulfill these constrain...
Radoslaw Szymanek, Krzysztof Kuchcinski