A statistical model for the purpose of logic cell timing analysis in the presence of process variations is presented. A new current-based cell delay model is utilized, which can a...
—An all n-p-n highly linear wide-bandwidth bipolar transconductor (Gm) stage is presented based on a variation of Caprio’s Quad. The high-frequency (HF) linearity of the improv...
— Lowering supply voltage is an effective technique for power reduction in memory design, however traditional memory cell design fails to operate, as shown in [3], [10], at ultra...
Jawar Singh, Jimson Mathew, Dhiraj K. Pradhan, Sar...
In this work, we characterize the performance of pico cell networks in presence of moving users. We model various traffic types between base-stations and mobiles as different typ...
We propose an algorithm based on singular value decomposition (SVD) to reduce the number of process variation variables. With few process variation variables, fault simulation and...