226 search results - page 23 / 46 » Variation-tolerant circuits: circuit solutions and technique... |
ICCAD
2009
IEEE
13 years 6 months ago
2009
IEEE
We propose a layout-driven test-architecture design and optimization technique for core-based system-on-chips (SoCs) that are fabricated using three-dimensional (3D) integration. ...
DATE
2008
IEEE
14 years 2 months ago
2008
IEEE
∗ Diagnosis is becoming a major concern with the rapid development of semiconductor memories. It provides information about the location of manufacturing defects in the memory, a...
TCAD
2002
13 years 8 months ago
2002
Abstract--This paper presents a solution to the problem of performance-driven buffered routing tree generation for VLSI circuits. Using a novel bottom-up construction algorithm and...
SAC
2010
ACM
13 years 8 months ago
2010
ACM
Voltage islanding technique in Network-on-Chip (NoC) can significantly reduce the computational energy consumption by scaling down the voltage levels of the processing elements (P...
DAC
2005
ACM
13 years 10 months ago
2005
ACM
On-chip supply networks are playing an increasingly important role for modern nanometer-scale designs. However, the ever growing sizes of power grids make the analysis problem ext...