226 search results - page 34 / 46 » Variation-tolerant circuits: circuit solutions and technique... |
ICCAD
2002
IEEE
14 years 4 months ago
2002
IEEE
Abstract— With the increasing cost of global communication onchip, high-performance designs for data-intensive applications require architectures that distribute hardware resourc...
ICCAD
2006
IEEE
14 years 4 months ago
2006
IEEE
Most existing buffering algorithms neglect the impact of inductance on circuit performance, which causes large error in circuit analysis and optimization. Even for the approaches...
ISCA
2003
IEEE
14 years 19 days ago
2003
IEEE
To achieve high instruction throughput, instruction schedulers must be capable of producing high-quality schedules that maximize functional unit utilization while at the same time...
ASPDAC
2007
ACM
13 years 11 months ago
2007
ACM
Abstract-- SAT sweeping is the process of merging two or more functionally equivalent nodes in a circuit by selecting one of them to represent all the other equivalent nodes. This ...
ICCD
2004
IEEE
14 years 4 months ago
2004
IEEE
The increasing clock frequencies in high-end industrial circuits bring new routing challenges that can not be handled by traditional algorithms. An important design automation pro...