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ICCAD
2001
IEEE
143views Hardware» more  ICCAD 2001»
14 years 4 months ago
Transient Power Management Through High Level Synthesis
The use of nanometer technologies is making it increasingly important to consider transient characteristics of a circuit’s power dissipation (e.g., peak power, and power gradien...
Vijay Raghunathan, Srivaths Ravi, Anand Raghunatha...
ICCD
2008
IEEE
142views Hardware» more  ICCD 2008»
14 years 1 months ago
Gate planning during placement for gated clock network
Abstract— Clock gating is a popular technique for reducing power dissipation in clock network. Although there have been numerous research efforts on clock gating, the previous ap...
Weixiang Shen, Yici Cai, Xianlong Hong, Jiang Hu
ISPD
2007
ACM
124views Hardware» more  ISPD 2007»
13 years 9 months ago
Accurate power grid analysis with behavioral transistor network modeling
In this paper, we propose fast and efficient techniques to analyze the power grid with accurate modeling of the transistor network. The solution techniques currently available for...
Anand Ramalingam, Giri Devarayanadurg, David Z. Pa...
VTC
2010
IEEE
140views Communications» more  VTC 2010»
13 years 5 months ago
To Cooperate or Not: A Capacity Perspective
Abstract—It is widely recognized that differential decode-andforward (DDF) cooperative transmission scheme is capable of providing a superior performance compared to classic dire...
Li Wang, Lingkun Kong, Soon Xin Ng, Lajos Hanzo
DAC
2009
ACM
14 years 8 months ago
Double patterning lithography friendly detailed routing with redundant via consideration
In double patterning lithography (DPL), coloring conflict and stitch minimization are the two main challenges. Post layout decomposition algorithm [1] [2]may not be enough to achi...
Kun Yuan, Katrina Lu, David Z. Pan