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» Verification-Aware Microprocessor Design

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ICES
2003
Springer

165views Hardware» more ICES 2003»

Speeding up Hardware Evolution: A Coprocessor for Evolutionary Algorithms

14 years 2 months ago

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This paper proposes a coprocessor architecture to speed up hardware evolution. It is designed to be implemented in an FPGA with an integrated microprocessor core. The coprocessor r...

Tillmann Schmitz, Steffen G. Hohmann, Karlheinz Me...

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ISVLSI
2007
IEEE

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Data Recovery Block Design for Impulse Modulated Power Line Communications in a Microprocessor

14 years 3 months ago

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Power line communications (PLC) using impulse ultra wideband (UWB) in a microprocessor had been proposed for ubiquitous access of internal nodes for test/debug purposes. In this p...

Rajesh Thirugnanam, Dong Sam Ha, T. M. Mak

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IOLTS
2006
IEEE

77views Hardware» more IOLTS 2006»

Design of a Robust 8-Bit Microprocessor to Soft Errors

14 years 3 months ago

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This work presents a fault-tolerant version of the

Rodrigo Possamai Bastos, Fernanda Lima Kastensmidt...

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