584 search results - page 63 / 117 » Verification-Aware Microprocessor Design |
ISSS
2002
IEEE
14 years 22 days ago
2002
IEEE
Adding a small loop cache to a microprocessor has been shown to reduce average instruction fetch energy for various sets of embedded system applications. With the advent of core-b...
DATE
2009
IEEE
14 years 2 months ago
2009
IEEE
—Localized heating-up creates thermal hotspots across the chip, with the integer register file ranked as the hottest unit in high-performance microprocessors. In this paper, we ...
ICPP
2008
IEEE
14 years 2 months ago
2008
IEEE
Numerical simulations in computational physics, biology, and finance, often require the use of high quality and efficient parallel random number generators. We design and optimi...
CODES
2007
IEEE
14 years 2 months ago
2007
IEEE
High-end biomedical applications are a good target for specificpurpose system-on-chip (SoC) implementations. Human heart electrocardiogram (ECG) real-time monitoring and analysis ...
DATE
2010
IEEE
14 years 28 days ago
2010
IEEE
—This paper presents a design space exploration of a selective load value prediction scheme suitable for energyaware Simultaneous Multi-Threaded (SMT) architectures. A load value...