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» Verification-Aware Microprocessor Design
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GLVLSI
2009
IEEE
186views VLSI» more  GLVLSI 2009»
14 years 2 months ago
Bitmask-based control word compression for NISC architectures
Implementing a custom hardware is not always feasible due to cost and time considerations. No instruction set computer (NISC) architecture is one of the promising direction to des...
Chetan Murthy, Prabhat Mishra
HPCA
2008
IEEE
14 years 2 months ago
Speculative instruction validation for performance-reliability trade-off
With reducing feature size, increasing chip capacity, and increasing clock speed, microprocessors are becoming increasingly susceptible to transient (soft) errors. Redundant multi...
Sumeet Kumar, Aneesh Aggarwal
ISVLSI
2007
IEEE
127views VLSI» more  ISVLSI 2007»
14 years 2 months ago
Asymmetrically Banked Value-Aware Register Files
Designing high-performance low-power register files is of critical importance to the continuation of current performance advances in wide-issue and deeply-pipelined superscalar m...
Shuai Wang, Hongyan Yang, Jie Hu, Sotirios G. Ziav...
DAC
2006
ACM
14 years 1 months ago
The zen of nonvolatile memories
Silicon technology based nonvolatile memories (NVM) have achieved widespread adoption for code and data storage applications. In the last 30 years, the traditional floating gate ...
Erwin J. Prinz
ASAP
2005
IEEE
142views Hardware» more  ASAP 2005»
14 years 1 months ago
Decimal Floating-Point Square Root Using Newton-Raphson Iteration
With continued reductions in feature size, additional functionality may be added to future microprocessors to boost the performance of important application domains. Due to growth...
Liang-Kai Wang, Michael J. Schulte