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» Verifying VLSI Circuits
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VLSID
2006
IEEE
129views VLSI» more  VLSID 2006»
14 years 11 months ago
Modeling and Reduction of Gate Leakage during Behavioral Synthesis of NanoCMOS Circuits
For a nanoCMOS of sub-65nm technology, where the gate oxide (SiO2) thickness is very low, the gate leakage is one of the major components of power dissipation. In this paper, we pr...
Saraju P. Mohanty, Elias Kougianos
VLSID
2001
IEEE
132views VLSI» more  VLSID 2001»
14 years 11 months ago
Accurate Power Macro-modeling Techniques for Complex RTL Circuits
This paper presents novel techniques for the cycle-accurate power macro-modeling of complex RTL components. The proposed techniques are based on the observation that RTL component...
Nachiketh R. Potlapally, Michael S. Hsiao, Anand R...
ISCAS
2006
IEEE
111views Hardware» more  ISCAS 2006»
14 years 5 months ago
CMOS analog iterative decoders using margin propagation circuits
Abstract- Analog iterative decoders offer several advantages over their digital counterparts in terms of speed and power -A- log-MAP consumption. The current state of art CMOS anal...
S. Chakrabartty
VLSID
2007
IEEE
91views VLSI» more  VLSID 2007»
14 years 11 months ago
Reusing Learned Information in SAT-based ATPG
The robustness of engines for ATPG has to be improved to cope with the growing size of circuits. Recently, SAT-based ATPG approaches have been shown to be very robust even on larg...
Görschwin Fey, Rolf Drechsler, Tim Warode
ICCD
2004
IEEE
106views Hardware» more  ICCD 2004»
14 years 8 months ago
A New Statistical Optimization Algorithm for Gate Sizing
— In this paper, we approach the gate sizing problem in VLSI circuits in the context of increasing variability of process and circuit parameters as technology scales into the nan...
Murari Mani, Michael Orshansky