1093 search results - page 125 / 219 » Verifying VLSI Circuits |
VLSID
2005
IEEE
14 years 9 months ago
2005
IEEE
This paper employs general multivariate normal distribution to develop a new efficient statistical timing analysis methodology. The paper presents the theoretical framework of the...
VLSID
2003
IEEE
14 years 9 months ago
2003
IEEE
This paper introduces a Built-In Self Test (BIST) structure referred to as Universal BIST (UBIST). The Test Pattern Generator (TPG) of the proposed UBIST is designed to generate an...
VLSID
2001
IEEE
14 years 9 months ago
2001
IEEE
A technique for signature based diagnosis using windows of different sizes is presented. It allows to obtain increased diagnostic information from a given test at a lower cost, wi...
ICCD
2005
IEEE
14 years 5 months ago
2005
IEEE
As CMOS technology scales deeper into the nanometer regime, factors such as leakage power and chip temperature emerge as critically important concerns for VLSI design. This paper,...
ICCD
2001
IEEE
14 years 5 months ago
2001
IEEE
CMOS Phase-locked loops (PLL) are ubiquitous in RF and mixed-signal integrated circuits. PLLs are very sensitive to noise fluctuations on the power and ground rails. In this paper...