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» Verifying VLSI Circuits

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DFT
1999
IEEE

72views VLSI» more DFT 1999»

Yield Estimation of VLSI Circuits with Downscaled Layouts

13 years 11 months ago

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This paper describes the yield estimation approach to layout scaling of submicron VLSI circuits. The presented method makes it feasible to find scaling factor of the IC design whi...

Witold A. Pleskacz

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DAC
1996
ACM

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Partitioning of VLSI Circuits and Systems

13 years 11 months ago

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Partitioning plays an increasingly important role in the design process of VLSI circuits and systems. There are partitioning to be solved on all levels of abstraction. The rapidly...

Frank M. Johannes

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DFT
2003
IEEE

106views VLSI» more DFT 2003»

Techniques for Transient Fault Sensitivity Analysis and Reduction in VLSI Circuits

14 years 24 days ago

Download euler.ecs.umass.edu

Transient faults in VLSI circuits could lead to disastrous consequences. With technology scaling, circuits are becoming increasingly vulnerable to transient faults. This papers pr...

Atul Maheshwari, Israel Koren, Wayne Burleson

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ICES
2000
Springer

105views Hardware» more ICES 2000»

Towards a Silicon Primordial Soup: A Fast Approach to Hardware Evolution with a VLSI Transistor Array

13 years 11 months ago

Download www.kip.uni-heidelberg.de

A new system for research on hardware evolution of analog VLSI circuits is proposed. The heart of the system is a CMOS chip providing an array of 16

Jörg Langeheine, Simon Fölling, Karlhein...

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