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» Verifying VLSI Circuits
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GLVLSI
2010
IEEE
210views VLSI» more  GLVLSI 2010»
14 years 2 months ago
Overscaling-friendly timing speculation architectures
Processors have traditionally been designed for the worst-case, resulting in designs that have high yields, but are expensive in terms of area and power. Better-than-worst-case (B...
John Sartori, Rakesh Kumar
VLSID
2007
IEEE
128views VLSI» more  VLSID 2007»
14 years 9 months ago
A Low Power Frequency Multiplication Technique for ZigBee Transciever
A low-power frequency multiplication technique, developed for ZigBee (IEEE 802.15.4) like applications is presented. We have provided an estimate for the power consumption for a g...
Jagdish Nayayan Pandey, Sudhir S. Kudva, Bharadwaj...
VLSID
2006
IEEE
92views VLSI» more  VLSID 2006»
14 years 9 months ago
A Wideband Frequency-Shift Keying Demodulator for Wireless Neural Stimulation Microsystems
: This paper presents a wideband frequency-shift keying (FSK) demodulator suitable for a digital data transmission chain of wireless neural stimulation microsystems such as cochlea...
Mian Dong, Chun Zhang, Songping Mai, Zhihua Wang, ...
VLSID
2005
IEEE
131views VLSI» more  VLSID 2005»
14 years 9 months ago
Efficient Space/Time Compression to Reduce Test Data Volume and Testing Time for IP Cores
Abstract-- We present two-dimensional (space/time) compression techniques that reduce test data volume and test application time for scan testing of intellectual property (IP) core...
Lei Li, Krishnendu Chakrabarty, Seiji Kajihara, Sh...
VLSID
2002
IEEE
115views VLSI» more  VLSID 2002»
14 years 9 months ago
Logic Synthesis for AND-XOR-OR Type Sense-Amplifying PLA
In this paper, a new logic synthesis method for an AND-XOR-OR type sense-amplifying PLA is proposed. An AND-XOR-OR type sense-amplifying PLA can achieve lowpower dissipation and h...
Hiroaki Yoshida, Hiroaki Yamaoka, Makoto Ikeda, Ku...