1093 search results - page 58 / 219 » Verifying VLSI Circuits |
VLSID
2005
IEEE
14 years 3 months ago
2005
IEEE
In this paper, we have proposed a design technique for the reversible circuit of Binary Coded Decimal (BCD) adder. The proposed circuit has the ability to add two 4bits binary var...
DFT
2003
IEEE
14 years 3 months ago
2003
IEEE
We describe a method for designing fault tolerant circuits based on an extension of a Concurrent Error Detection (CED) technique. The proposed extension combines parity check code...
ISVLSI
2006
IEEE
14 years 4 months ago
2006
IEEE
FinFET technology has been proposed as a promising alternative for deep sub-micro bulk CMOS technology, because of its better scalability. Previous work have studied the performan...
GLVLSI
2009
IEEE
2009
IEEE
On the complexity of graph cuboidal dual problems for 3-D floorplanning of integrated circuit design
14 years 4 months ago
This paper discusses the impact of migrating from 2-D to 3-D on floorplanning and placement. By looking at a basic formulation of graph cuboidal dual problem, we show that the 3-...
ISVLSI
2008
IEEE
14 years 4 months ago
2008
IEEE
Subthreshold circuits exhibit ultra-low energy per operation at the expense of increased delay. In this contribution, the impact of technology scaling on digital subthreshold circ...