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» Verifying VLSI Circuits
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GLVLSI
2006
IEEE
193views VLSI» more  GLVLSI 2006»
14 years 4 months ago
Optimizing noise-immune nanoscale circuits using principles of Markov random fields
As CMOS devices and operating voltages are scaled down, noise and defective devices will impact the reliability of digital circuits. Probabilistic computing compatible with CMOS o...
Kundan Nepal, R. Iris Bahar, Joseph L. Mundy, Will...
ICCAD
1996
IEEE
151views Hardware» more  ICCAD 1996»
14 years 2 months ago
Expected current distributions for CMOS circuits
The analysis of CMOS VLSI circuit switching current has become an increasingly important and difficult task from both a VLSI design and simulation software perspective. This paper...
Dennis J. Ciplickas, Ronald A. Rohrer
GLVLSI
2009
IEEE
113views VLSI» more  GLVLSI 2009»
14 years 1 months ago
Reducing parity generation latency through input value aware circuits
1 Soft errors caused by cosmic particles and radiation emitted by the packaging are an important problem in contemporary microprocessors. Parity bits are used to detect single bit ...
Yusuf Osmanlioglu, Y. Onur Koçberber, Oguz ...
GLVLSI
2009
IEEE
128views VLSI» more  GLVLSI 2009»
14 years 1 months ago
Impact of lithography-friendly circuit layout
Current lithography techniques use a light wavelength of 193nm to print sub-65nm features. This introduces process variations which cause mismatches between desired and actual waf...
Pratik J. Shah, Jiang Hu
GLVLSI
2005
IEEE
186views VLSI» more  GLVLSI 2005»
14 years 3 months ago
An FPGA design of AES encryption circuit with 128-bit keys
This paper addresses a pipelined partial rolling (PPR) architecture for the AES encryption. The key technique is the PPR architecture, which is suitable for FPGA implementation. U...
Hui Qin, Tsutomu Sasao, Yukihiro Iguchi