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» Verifying VLSI Circuits
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GLVLSI
2010
IEEE
296views VLSI» more  GLVLSI 2010»
13 years 10 months ago
AOP-based high-level power estimation in SystemC
The paper presents a novel high-level power modeling and estimation framework. The approach is based on a synergic integration of aspect-oriented programming(AOP) and SystemC. Mac...
Feng Liu, QingPing Tan, Xiaoyu Song, Naeem Abbasi
DAC
2000
ACM
14 years 11 months ago
Formal verification of iterative algorithms in microprocessors
Contemporary microprocessors implement many iterative algorithms. For example, the front-end of a microprocessor repeatedly fetches and decodes instructions while updating interna...
Mark Aagaard, Robert B. Jones, Roope Kaivola, Kath...
GLVLSI
2009
IEEE
155views VLSI» more  GLVLSI 2009»
14 years 4 months ago
Buffer design and optimization for lut-based structured ASIC design styles
The interconnection delay of pre-fabricated design style dominates circuit delay due to the heavily downstream capacitance. Buffer insertion is a widely used technique to split o...
Po-Yang Hsu, Shu-Ting Lee, Fu-Wei Chen, Yi-Yu Liu
ICC
2007
IEEE
115views Communications» more  ICC 2007»
14 years 1 months ago
Super-Wideband SSN Suppression in High-Speed Digital Communication Systems by Using Multi-Via Electromagnetic Bandgap Structures
With the advance of semiconductor manufacturing, There are many approaches to deal with these problems. EDA, and VLSI design technologies, circuits with even higher Adding discrete...
MuShui Zhang, YuShan Li, LiPing Li, Chen Jia
VLSID
2002
IEEE
116views VLSI» more  VLSID 2002»
14 years 10 months ago
A Design of Analog C-Matrix Circuits Used for Signal/Data Processing
Various calculation of matrices and vectors has been used in many digital signal processing systems. Although the calculation simply repeats multiplication and addition, the reite...
Takayuki Sugawara, Yoshikazu Miyanaga, Norinobu Yo...