We model and verify analog designs in the presence of noise and process variation using an automated theorem prover, MetiTarski. Due to the statistical nature of noise, we propose ...
Rajeev Narayanan, Behzad Akbarpour, Mohamed H. Zak...
For a logic design with level-sensitive latches, we need to validate timing signal paths which may flush through several latches. We developed efficient algorithms based on the mo...
A new technique has been proposed to improve the transient behavior of the on-chip/embedded voltage regulator. It is realized by introducing a dynamic leakage path at the driver s...
Over the last five years the VLSI Placement community achieved great strides in the understanding of placement problems, developed new high-performance algorithms, and achieved i...
Saurabh N. Adya, Mehmet Can Yildiz, Igor L. Markov...
Mixed Vt has been widely used to control leakage without affecting circuit performance. However, current approaches target the combinational circuits even though sequential elemen...