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» Verifying VLSI Circuits
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DATE
2010
IEEE
168views Hardware» more  DATE 2010»
14 years 2 months ago
Formal verification of analog circuits in the presence of noise and process variation
We model and verify analog designs in the presence of noise and process variation using an automated theorem prover, MetiTarski. Due to the statistical nature of noise, we propose ...
Rajeev Narayanan, Behzad Akbarpour, Mohamed H. Zak...
ICCAD
1994
IEEE
82views Hardware» more  ICCAD 1994»
14 years 2 months ago
A timing analysis algorithm for circuits with level-sensitive latches
For a logic design with level-sensitive latches, we need to validate timing signal paths which may flush through several latches. We developed efficient algorithms based on the mo...
Jin-fuw Lee, Donald T. Tang, C. K. Wong
VLSID
2005
IEEE
117views VLSI» more  VLSID 2005»
14 years 10 months ago
On-Chip Voltage Regulator with Improved Transient Response
A new technique has been proposed to improve the transient behavior of the on-chip/embedded voltage regulator. It is realized by introducing a dynamic leakage path at the driver s...
Ashis Maity, R. G. Raghavendra, Pradip Mandal
ISPD
2003
ACM
92views Hardware» more  ISPD 2003»
14 years 3 months ago
Benchmarking for large-scale placement and beyond
Over the last five years the VLSI Placement community achieved great strides in the understanding of placement problems, developed new high-performance algorithms, and achieved i...
Saurabh N. Adya, Mehmet Can Yildiz, Igor L. Markov...
DAC
2007
ACM
14 years 2 months ago
Skewed Flip-Flop Transformation for Minimizing Leakage in Sequential Circuits
Mixed Vt has been widely used to control leakage without affecting circuit performance. However, current approaches target the combinational circuits even though sequential elemen...
Jun Seomun, Jaehyun Kim, Youngsoo Shin