26 search results - page 5 / 6 » Voltage island aware floorplanning for power and timing opti... |
TPDS
2010
13 years 5 months ago
2010
Abstract—A rising horizon in chip fabrication is the 3D integration technology. It stacks two or more dies vertically with a dense, highspeed interface to increase the device den...
VLSID
2002
IEEE
14 years 7 months ago
2002
IEEE
Among the many techniques for system-level power management, it is not currently possible to guarantee timing constraints and have a comprehensive system model at the same time. S...
ISQED
2009
IEEE
14 years 2 months ago
2009
IEEE
We propose a novel design flow for mismatch and processvariation aware optimization of nanoscale CMOS Active Pixel Sensor (APS) arrays. As a case study, an 8 × 8 APS array is de...
GLVLSI
2009
IEEE
13 years 11 months ago
2009
IEEE
In this paper, we present the design of a P4 (Power-PerformanceProcess-Parasitic) aware voltage controlled oscillator (VCO) at nanoCMOS technologies. Through simulations, we have ...
DAC
2006
ACM
14 years 8 months ago
2006
ACM
Deploying multiple supply voltages (multi-Vdds) on one chip is an important technique to reduce dynamic power consumption. In this work we present an optimality study for resource...