16 search results - page 2 / 4 » Way-predicting set-associative cache for high performance an... |
CF
2011
ACM
12 years 8 months ago
2011
ACM
Ubiquitous computing has become a very popular paradigm. The most suitable technological solution for those systems consists of using hybrid processors able to operate at high vol...
ICCAD
2009
IEEE
13 years 6 months ago
2009
IEEE
The emerging Spin Torque Transfer memory (STT-RAM) is a promising candidate for future on-chip caches due to STT-RAM's high density, low leakage, long endurance and high acce...
LCTRTS
2007
Springer
14 years 2 months ago
2007
Springer
Set-associative caches are traditionally managed using hardwarebased lookup and replacement schemes that have high energy overheads. Ideally, the caching strategy should be tailor...
ISCA
1997
IEEE
14 years 3 days ago
1997
IEEE
Portable systems demand energy efficiency in order to maximize battery life. IRAM architectures, which combine DRAM and a processor on the same chip in a DRAM process, are more en...
DAC
2002
ACM
14 years 9 months ago
2002
ACM
In this paper we propose a novel integrated circuit and architectural level technique to reduce leakage power consumption in high performance cache memories using single Vt (trans...