94 search results - page 11 / 19 » Wire width planning for interconnect performance optimizatio... |
ISCA
2007
IEEE
14 years 1 months ago
2007
IEEE
The ever increasing sizes of on-chip caches and the growing domination of wire delay necessitate significant changes to cache hierarchy design methodologies. Many recent proposal...
ICCAD
2006
IEEE
14 years 4 months ago
2006
IEEE
With shrinking feature size and growing integration density in the Deep Sub-Micron technologies, the global buses are fast becoming the “weakest-links” in VLSI design. They ha...
HPCA
2003
IEEE
14 years 7 months ago
2003
IEEE
As the level of chip integration continues to advance at a fast pace, the desire for efficient interconnects-whether on-chip or off-chip--is rapidly increasing. Traditional interc...
ASPDAC
2004
ACM
14 years 24 days ago
2004
ACM
As the process technology advances into the deep submicron era, interconnect plays a dominant role in determining circuit performance and signal integrity. Buffer insertion is one...
TVLSI
2002
13 years 7 months ago
2002
Abstract--The design of high integrity, area efficient power distribution grids has become of practical importance as the portion of on-chip interconnect resources dedicated to pow...