94 search results - page 15 / 19 » Wire width planning for interconnect performance optimizatio... |
DATE
2006
IEEE
14 years 1 months ago
2006
IEEE
The existence of non-uniform thermal gradients on the substrate in high performance IC’s can significantly impact the performance of global on-chip interconnects. This issue is...
ISPD
1998
ACM
13 years 11 months ago
1998
ACM
—High-frequency circuits are notoriously difficult to lay out because of the tight coupling between device-level placement and wiring. Given that successful electrical performan...
DAC
2008
ACM
14 years 8 months ago
2008
ACM
A low power passive equalizer using RL terminator is proposed and optimized in this work. The equalizer includes an inductor in series with the resistive terminator, which boosts ...
ASPDAC
2006
ACM
14 years 1 months ago
2006
ACM
— Buffer insertion is an effective technique to reduce interconnect delay. In this paper, we give a simple O(mn) time algorithm for optimal buffer insertion, where m is the numbe...
ISPD
2005
ACM
14 years 27 days ago
2005
ACM
The sustained progress of VLSI technology has altered the landscape of routing which is a major physical design stage. For timing driven routings, traditional approaches which con...