564 search results - page 101 / 113 » Wireplanning in logic synthesis |
ICCAD
2008
IEEE
14 years 4 months ago
2008
IEEE
Functional decomposition is a fundamental operation in logic synthesis. Prior BDD-based approaches to functional decomposition suffer from the memory explosion problem and do not...
ICCAD
2006
IEEE
14 years 4 months ago
2006
IEEE
In a synchronous finite state machine (FSM), huge current peaks are often observed at the moment of state transition. Previous low power state encoding algorithms focus on the red...
ICCAD
2004
IEEE
14 years 4 months ago
2004
IEEE
— This paper presents two contributions. The first is an incremental placement algorithm for placement-aware logic synthesis along with a proof of optimality. The algorithm can ...
IOLTS
2009
IEEE
14 years 2 months ago
2009
IEEE
— The paper deals with designing fault tolerant finite state machines (FSMs) by nanoelectronic programmable logic arrays (PLAs). Two main critical parameters of the fault toleran...
IPPS
2009
IEEE
14 years 2 months ago
2009
IEEE
We propose a novel design estimation method for adaptive streaming applications to be implemented on a partially reconfigurable FPGA. Based on experimental results we enable accu...