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» Wireplanning in logic synthesis
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DATE
2006
IEEE
88views Hardware» more  DATE 2006»
14 years 1 months ago
Enabling fine-grain leakage management by voltage anchor insertion
Functional unit shutdown based on MTCMOS devices is effective for leakage reduction in aggressively scaled technologies. However, the applicability of MTCMOS-based shutdown in a s...
Pietro Babighian, Luca Benini, Alberto Macii, Enri...
DATE
2006
IEEE
124views Hardware» more  DATE 2006»
14 years 1 months ago
Timing-driven cell layout de-compaction for yield optimization by critical area minimization
This paper proposes a yield optimization method for standard-cells under timing constraints. Yield-aware logic synthesis and physical optimization require yield-enhanced standard ...
Tetsuya Iizuka, Makoto Ikeda, Kunihiro Asada
ASAP
2005
IEEE
142views Hardware» more  ASAP 2005»
14 years 1 months ago
Decimal Floating-Point Square Root Using Newton-Raphson Iteration
With continued reductions in feature size, additional functionality may be added to future microprocessors to boost the performance of important application domains. Due to growth...
Liang-Kai Wang, Michael J. Schulte
AADEBUG
2005
Springer
14 years 27 days ago
An integrated debugging environment for reprogrammble hardware systems
Reprogrammable hardware systems are traditionally very difficult to debug due to their high level of parallelism. In our solution to this problem, features are inserted into the u...
Kevin Camera, Hayden Kwok-Hay So, Robert W. Broder...
DNA
2004
Springer
14 years 22 days ago
DNA Hybridization Catalysts and Catalyst Circuits
Practically all of life’s molecular processes, from chemical synthesis to replication, involve enzymes that carry out their functions through the catalysis of metastable fuels in...
Georg Seelig, Bernard Yurke, Erik Winfree