564 search results - page 77 / 113 » Wireplanning in logic synthesis |
ISSS
1995
IEEE
14 years 2 months ago
1995
IEEE
Designers of embedded systems are facing ever tighter constraintson design time, but computer aided design tools for embedded systems have not kept pace with these trends. The Chi...
TCAD
2002
13 years 10 months ago
2002
Many tasks in CAD, such as equivalence checking, property checking, logic synthesis, and false paths analysis require efficient Boolean reasoning for problems derived from circuits...
ASPDAC
2010
ACM
13 years 9 months ago
2010
ACM
Abstract-- Optimizing blocks in a System-on-Chip (SoC) circuit is becoming more and more important nowadays due to the use of third-party Intellectual Properties (IPs) and reused d...
DAC
2008
ACM
14 years 12 months ago
2008
ACM
This paper addresses the problem of computational error modeling and analysis. Choosing different word-lengths for each functional unit in hardware implementations of numerical al...
DAC
2006
ACM
14 years 11 months ago
2006
ACM
In this paper we propose a new communication synthesis approach targeting systems with sequential communication media (SCM). Since SCMs require that the reading sequence and writi...