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» Wireplanning in logic synthesis
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DAC
2003
ACM
14 years 9 months ago
Dynamic hardware/software partitioning: a first approach
Partitioning an application among software running on a microprocessor and hardware co-processors in on-chip configurable logic has been shown to improve performance and energy co...
Greg Stitt, Roman L. Lysecky, Frank Vahid
DAC
2004
ACM
14 years 9 months ago
Design automation for mask programmable fabrics
Programmable circuit design has played an important role in improving design productivity over the last few decades. By imposing structure on the design, efficient automation of s...
Narendra V. Shenoy, Jamil Kawa, Raul Camposano
ASPDAC
2004
ACM
107views Hardware» more  ASPDAC 2004»
14 years 1 months ago
Minimization of the expected path length in BDDs based on local changes
— In many verification tools methods for functional simulation based on reduced ordered Binary Decision Diagrams (BDDs) are used. The evaluation time for a BDD can be crucial an...
Rüdiger Ebendt, Wolfgang Günther, Rolf D...
ERSA
2004
134views Hardware» more  ERSA 2004»
13 years 10 months ago
A High Performance Application Representation for Reconfigurable Systems
Modern reconfigurable computing systems feature powerful hybrid architectures with multiple microprocessor cores, large reconfigurable logic arrays and distributed memory hierarch...
Wenrui Gong, Gang Wang, Ryan Kastner
ISCA
1999
IEEE
105views Hardware» more  ISCA 1999»
14 years 24 days ago
The Program Decision Logic Approach to Predicated Execution
Modern compilers must expose sufficient amounts of Instruction-Level Parallelism (ILP) to achieve the promised performance increases of superscalar and VLIW processors. One of the...
David I. August, John W. Sias, Jean-Michel Puiatti...