85 search results - page 13 / 17 » Wiring edge-disjoint layouts |
EURODAC
1994
IEEE
13 years 11 months ago
1994
IEEE
Undetectable shorts may decrease the long term reliability of a circuit, cause intermittent failures, add noise and delay, or increase test pattern generation costs. This paper de...
ICCAD
2009
IEEE
13 years 5 months ago
2009
IEEE
We propose a layout-driven test-architecture design and optimization technique for core-based system-on-chips (SoCs) that are fabricated using three-dimensional (3D) integration. ...
ICCD
2004
IEEE
14 years 4 months ago
2004
IEEE
I/O placement has always been a concern in modern IC design. Due to flip-chip technology, I/O can be placed throughout the whole chip without long wires from the periphery of the...
ICCAD
2005
IEEE
14 years 4 months ago
2005
IEEE
Separate optimizations of logic and layout have been thoroughly studied in the past and are well documented for common benchmarks. However, to be competitive, modern circuit optim...
ASPDAC
2007
ACM
13 years 11 months ago
2007
ACM
-- Physical synthesis is a relatively young field in Electronic Design Automation. Many published optimizations for physical synthesis end up hurting the final result, often by neg...