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ISCA
2010
IEEE
199views Hardware» more  ISCA 2010»
14 years 21 days ago
A case for FAME: FPGA architecture model execution
Given the multicore microprocessor revolution, we argue that the architecture research community needs a dramatic increase in simulation capacity. We believe FPGA Architecture Mod...
Zhangxi Tan, Andrew Waterman, Henry Cook, Sarah Bi...
ENTCS
2008
138views more  ENTCS 2008»
13 years 8 months ago
Compositionality of Statically Scheduled IP
Timing Closure in presence of long global wire interconnects is one of the main current issues in System-onChip design. One proposed solution to the Timing Closure problem is Late...
Julien Boucaron, Jean-Vivien Millo
DAC
2003
ACM
14 years 8 months ago
Design flow for HW / SW acceleration transparency in the thumbpod secure embedded system
This paper describes a case study and design flow of a secure embedded system called ThumbPod, which uses cryptographic and biometric signal processing acceleration. It presents t...
David Hwang, Bo-Cheng Lai, Patrick Schaumont, Kazu...
JSS
2007
86views more  JSS 2007»
13 years 7 months ago
Performance evaluation of UML design with Stochastic Well-formed Nets
The paper presents a method to compute performance metrics (response time, sojourn time, throughput) on Unified Modeling Language design. The method starts with UML design annota...
Simona Bernardi, José Merseguer
DATE
2010
IEEE
139views Hardware» more  DATE 2010»
14 years 6 days ago
Pareto efficient design for reconfigurable streaming applications on CPU/FPGAs
We present a Pareto efficient design method for multi-dimensional optimization of run-time reconfigurable streaming applications on CPU/FPGA platforms, which automatically allocate...
Jun Zhu, Ingo Sander, Axel Jantsch