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ICCD
2004
IEEE
129views Hardware» more  ICCD 2004»
14 years 4 months ago
Cache Array Architecture Optimization at Deep Submicron Technologies
A cache access time model, PRACTICS (PRedictor of Access and Cycle TIme for Cache Stack), has been developed to optimize the memory array architecture for the minimum access and c...
Annie (Yujuan) Zeng, Kenneth Rose, Ronald J. Gutma...
MICRO
2002
IEEE
104views Hardware» more  MICRO 2002»
14 years 20 days ago
Compiling for instruction cache performance on a multithreaded architecture
Instruction cache aware compilation seeks to lay out a program in memory in such a way that cache conflicts between procedures are minimized. It does this through profile-driven...
Rakesh Kumar, Dean M. Tullsen
VLDB
1994
ACM
148views Database» more  VLDB 1994»
13 years 12 months ago
Cache Conscious Algorithms for Relational Query Processing
The current main memory (DRAM) access speeds lag far behind CPU speeds. Cache memory, made of static RAM, is being used in today's architectures to bridge this gap. It provid...
Ambuj Shatdal, Chander Kant, Jeffrey F. Naughton
ASPLOS
1991
ACM
13 years 11 months ago
LimitLESS Directories: A Scalable Cache Coherence Scheme
Caches enhance the performance of multiprocessors by reducing network trac and average memory access latency. However, cache-based systems must address the problem of cache coher...
David Chaiken, John Kubiatowicz, Anant Agarwal
CGO
2006
IEEE
14 years 1 months ago
A Cross-Architectural Interface for Code Cache Manipulation
Software code caches help amortize the overhead of dynamic binary transformation by enabling reuse of transformed code. Since code caches contain a potentiallyaltered copy of ever...
Kim M. Hazelwood, Robert S. Cohn