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DAC
2002
ACM
14 years 10 months ago
River PLAs: a regular circuit structure
A regular circuit structure called a River PLA and its reconfigurable version, Glacier PLA, are presented. River PLAs provide greater regularity than circuits implemented with sta...
Fan Mo, Robert K. Brayton
DAC
2002
ACM
14 years 10 months ago
Petri net modeling of gate and interconnect delays for power estimation
In this paper, a new type of Petri net called Hierarchical Colored Hardware Petri net, to model real-delay switching activity for power estimation is proposed. The logic circuit i...
Ashok K. Murugavel, N. Ranganathan
DAC
2002
ACM
14 years 10 months ago
Efficient code synthesis from extended dataflow graphs for multimedia applications
This paper presents efficient automatic code synthesis techniques from dataflow graphs for multimedia applications. Since multimedia applications require large size buffers contai...
Hyunok Oh, Soonhoi Ha
DAC
2002
ACM
14 years 10 months ago
A general probabilistic framework for worst case timing analysis
CT The traditional approach to worst-case static-timing analysis is becoming unacceptably conservative due to an ever-increasing number of circuit and process effects. We propose a...
Michael Orshansky, Kurt Keutzer
DAC
2002
ACM
14 years 10 months ago
Transformation based communication and clock domain refinement for system design
The ForSyDe methodology has been developed for system level design. In this paper we present formal transformation methods for the refinement of an abstract and formal system mode...
Ingo Sander, Axel Jantsch