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ASPDAC
2000
ACM
104views Hardware» more  ASPDAC 2000»
13 years 11 months ago
Design of digital neural cell scheduler for intelligent IB-ATM switch
— We present the architecture of the ATM banyan switch composed of pattern process and high-speed digital neural cell scheduler. An input buffer type ATM switch with a window-bas...
J.-K. Lee, Seung-Min Lee, Mike Myung-Ok Lee, D.-W....
DAC
2000
ACM
14 years 7 months ago
Hardware-software co-design of embedded reconfigurable architectures
In this paper we describe a new hardware/software partitioning approach for embedded reconfigurable architectures consisting of a general-purpose processor (CPU), a dynamically re...
Yanbing Li, Tim Callahan, Ervan Darnell, Randolph ...
FCCM
2008
IEEE
205views VLSI» more  FCCM 2008»
14 years 1 months ago
Credit Risk Modelling using Hardware Accelerated Monte-Carlo Simulation
The recent turmoil in global credit markets has demonstrated the need for advanced modelling of credit risk, which can take into account the effects of changing economic condition...
David B. Thomas, Wayne Luk
ASYNC
2000
IEEE
86views Hardware» more  ASYNC 2000»
13 years 11 months ago
An On-Chip Dynamically Recalibrated Delay Line for Embedded Self-Timed Systems
Self-timed systems often have to communicate with their environment through a clocked interface. For example, off-chip memory may require clocking and this can reduce the benefit...
George S. Taylor, Simon W. Moore, Steve Wilcox, Pe...
DATE
2000
IEEE
89views Hardware» more  DATE 2000»
13 years 11 months ago
A System-Level Synthesis Algorithm with Guaranteed Solution Quality
Recently a number of heuristic based system-level synthesis algorithms have been proposed. Though these algorithms quickly generate good solutions, how close these solutions are t...
U. Nagaraj Shenoy, Prithviraj Banerjee, Alok N. Ch...