Sciweavers

95 search results - page 2 / 19
» fpga 2000
Sort
View
FPGA
2000
ACM
177views FPGA» more  FPGA 2000»
13 years 10 months ago
Automatic generation of FPGA routing architectures from high-level descriptions
In this paper we present a "high-level" FPGA architecture description language which lets FPGA architects succinctly and quickly describe an FPGA routing architecture. W...
Vaughn Betz, Jonathan Rose
IOLTS
2000
IEEE
84views Hardware» more  IOLTS 2000»
13 years 11 months ago
Self-Testing of FPGA Delay Faults in the System Environment
We propose a procedure for self-testing of an FPGA programmed to implement a user-defined function. The procedure is intended to improve the detectability of FPGA delay faults. Th...
Andrzej Krasniewski
ESTIMEDIA
2004
Springer
13 years 12 months ago
A hardware accelerator IP for EBCOT Tier-1 coding in JPEG2000 Standard
We proposed a hardware accelerator IP for the Tier-1 portion of Embedded Block Coding with Optimal Truncation (EBCOT) used in the JPEG2000 next generation image compression standa...
Tien-Wei Hsieh, Youn-Long Lin
ISCAS
2005
IEEE
156views Hardware» more  ISCAS 2005»
14 years 5 days ago
Optimal 2 sub-bank memory architecture for bit plane coder of JPEG2000
—JPEG2000 image compression standard is designed to cater the needs of a large span of applications including numerous consumer products. However, its use is still restricted due...
Amit Kumar Gupta, Saeid Nooshabadi, David S. Taubm...
ICRA
2010
IEEE
245views Robotics» more  ICRA 2010»
13 years 5 months ago
2000 fps real-time vision system with high-frame-rate video recording
—This paper introduces a high-speed vision system called IDP Express, which can execute real-time image processing and high frame rate video recording simultaneously. In IDP Expr...
Idaku Ishii, Tetsuro Tatebe, Qingyi Gu, Yuta Moriu...