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FPL
2003
Springer
95views Hardware» more  FPL 2003»
14 years 20 days ago
A Model for Hardware Realization of Kernel Loops
Abstract. Hardware realization of kernel loops holds the promise of accelerating the overall application performance and is therefore an important part of the synthesis process. In...
Jirong Liao, Weng-Fai Wong, Tulika Mitra
FPL
2003
Springer
100views Hardware» more  FPL 2003»
14 years 20 days ago
An Extensible, System-On-Programmable-Chip, Content-Aware Internet Firewall
An extensible firewall has been implemented that performs packet filtering, content scanning, and per-flow queuing of Internet packets at Gigabit/second rates. The firewall use...
John W. Lockwood, Christopher E. Neely, Christophe...
FPL
2003
Springer
100views Hardware» more  FPL 2003»
14 years 20 days ago
Two Approaches for a Single-Chip FPGA Implementation of an Encryptor/Decryptor AES Core
In this paper we present a single-chip FPGA full encryptor/decryptor core design of the AES algorithm. Our design performs all of them, encryption, decryption and key scheduling pr...
Nazar A. Saqib, Francisco Rodríguez-Henr&ia...
FPL
2003
Springer
161views Hardware» more  FPL 2003»
14 years 20 days ago
Laura: Leiden Architecture Research and Exploration Tool
At Leiden Embedded Research Center (LERC), we are building a tool chain called Compaan/Laura that allows us to map fast and efficiently applications written in Matlab onto recon...
Claudiu Zissulescu, Todor Stefanov, Bart Kienhuis,...
FPL
2003
Springer
114views Hardware» more  FPL 2003»
14 years 20 days ago
Power Analysis of FPGAs: How Practical is the Attack?
Recent developments in information technologies made the secure transmission of digital data a critical design point. Large data flows have to be exchanged securely and involve en...
François-Xavier Standaert, Loïc van Ol...