Sciweavers

106 search results - page 20 / 22
» itc 2003
Sort
View
ITC
2003
IEEE
139views Hardware» more  ITC 2003»
14 years 3 months ago
Fault Pattern Oriented Defect Diagnosis for Memories
Failure analysis (FA) and diagnosis of memory cores plays a key role in system-on-chip (SOC) product development and yield ramp-up. Conventional FA based on bitmaps and the experi...
Chih-Wea Wang, Kuo-Liang Cheng, Jih-Nung Lee, Yung...
ITC
2003
IEEE
127views Hardware» more  ITC 2003»
14 years 3 months ago
Using Logic Models To Predict The Detection Behavior Of Statistical Timing Defects
In this paper, we study the possibility of using logic defect-level prediction models to predict the detection behavior of statistical timing defects. We compare two known logic m...
Li-C. Wang, Angela Krstic, Leonard Lee, Kwang-Ting...
ICCAD
2003
IEEE
105views Hardware» more  ICCAD 2003»
14 years 6 months ago
TAM Optimization for Mixed-Signal SOCs using Analog Test Wrappers
We present a new approach for TAM optimization and test scheduling in the modular testing of mixed-signal SOCs. A test planning approach for digital SOCs is extended to handle ana...
Anuja Sehgal, Sule Ozev, Krishnendu Chakrabarty
ATS
2003
IEEE
98views Hardware» more  ATS 2003»
14 years 3 months ago
Automatic Design Validation Framework for HDL Descriptions via RTL ATPG
We present a framework for high-level design validation using an efficient register-transfer level (RTL) automatic test pattern generator (ATPG). The RTL ATPG generates the test ...
Liang Zhang, Michael S. Hsiao, Indradeep Ghosh
DATE
2003
IEEE
130views Hardware» more  DATE 2003»
14 years 3 months ago
A Technique for High Ratio LZW Compression
Reduction of both the test suite size and the download time of test vectors is important in today's System-On-a-Chip designs. In this paper, a method for compressing the scan...
Michael J. Knieser, Francis G. Wolff, Christos A. ...