This paper describes the implementation of a test pattern language using STIL [1], the IEEE Standard Test Interface Language (1450-1999), in a next generation, open architecture A...
The objective of this paper is to present an infrastructure IP (I-IP) designed to characterize yield loss in the process back-end. The I-IP structure is described in using a botto...
Knowing, that the threshold voltage of the EEPROM memory cells is a key parameter to determine the overall performance of the memory, a build in structure to extract this informat...
This paper describes a system for performing high precision IDDQ measurement of CMOS ICs having a large peak current during operation. Although the measurement rate is at a low sp...
We present a measurement module that computes the charge from the transient supply current and provides a digital value of this magnitude. The module is constructed to provide a f...
Bartomeu Alorda, B. Bloechel, Ali Keshavarzi, Jaum...