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ICCD
2005
IEEE
246views Hardware» more  ICCD 2005»
14 years 5 months ago
H-SIMD Machine: Configurable Parallel Computing for Matrix Multiplication
FPGAs (Field-Programmable Gate Arrays) are often used as coprocessors to boost the performance of dataintensive applications [1, 2]. However, mapping algorithms onto multimillion-...
Xizhen Xu, Sotirios G. Ziavras
ICRA
2005
IEEE
186views Robotics» more  ICRA 2005»
14 years 2 months ago
Experimental Studies of a Neural Oscillator for Biped Locomotion with QRIO
— Recently, there has been a growing interest in biologically inspired biped locomotion control with Central Pattern Generator (CPG). However, few experimental attempts on real h...
Gen Endo, Jun Nakanishi, Jun Morimoto, Gordon Chen...
ISCAS
2005
IEEE
165views Hardware» more  ISCAS 2005»
14 years 2 months ago
An area-efficient and protected network interface for processing-in-memory systems
Abstract- This paper describes the implementation of an areaefficient and protected user memory-mapped network interface, the pbuf (Parcel Buffer), for the Data IntensiVe Architect...
Sumit D. Mediratta, Craig S. Steele, Jeff Sondeen,...
ISLPED
2005
ACM
99views Hardware» more  ISLPED 2005»
14 years 2 months ago
A low-power bus design using joint repeater insertion and coding
In this paper, we propose joint repeater insertion and crosstalk avoidance coding as a low-power alternative to repeater insertion for global bus design in nanometer technologies....
Srinivasa R. Sridhara, Naresh R. Shanbhag
DAC
2005
ACM
14 years 9 months ago
Hardware speech recognition for user interfaces in low cost, low power devices
We propose a system architecture for real-time hardware speech recognition on low-cost, power-constrained devices. The system is intended to support real-time speech-based user in...
Sergiu Nedevschi, Rabin K. Patra, Eric A. Brewer