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ASPDAC
2007
ACM
119views Hardware» more  ASPDAC 2007»
15 years 8 months ago
Optimum Prefix Adders in a Comprehensive Area, Timing and Power Design Space
Parallel prefix adder is the most flexible and widely-used binary adder for ASIC designs. Many high-level synthesis techniques have been developed to find optimal prefix structures...
Jianhua Liu, Yi Zhu, Haikun Zhu, Chung-Kuan Cheng,...
ASPDAC
2007
ACM
116views Hardware» more  ASPDAC 2007»
15 years 8 months ago
MODLEX: A Multi Objective Data Layout EXploration Framework for Embedded Systems-on-Chip
The memory subsystem is a major contributor to the performance, power, and area of complex SoCs used in feature rich multimedia products. Hence, memory architecture of the embedded...
T. S. Rajesh Kumar, C. P. Ravikumar, R. Govindaraj...
ASYNC
2007
IEEE
129views Hardware» more  ASYNC 2007»
15 years 8 months ago
Formal Verification of CHP Specifications with CADP Illustration on an Asynchronous Network-on-Chip
Few formal verification techniques are currently available for asynchronous designs. In this paper, we describe a new approach for the formal verification of asynchronous architec...
Gwen Salaün, Wendelin Serwe, Yvain Thonnart, ...
ATAL
2007
Springer
15 years 8 months ago
A multilateral multi-issue negotiation protocol
In this paper, we present a new protocol to address multilateral multi-issue negotiation in a cooperative context. We consider complex dependencies between multiple issues by mode...
Miniar Hemaissia, Amal El Fallah-Seghrouchni, Chri...
ATAL
2007
Springer
15 years 8 months ago
On the benefits of cheating by self-interested agents in vehicular networks
As more and more cars are equipped with GPS and Wi-Fi transmitters, it becomes easier to design systems that will allow cars to interact autonomously with each other, e.g., regard...
Raz Lin, Sarit Kraus, Yuval Shavitt
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