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ASPDAC
2009
ACM
141views Hardware» more  ASPDAC 2009»
13 years 10 months ago
Adaptive inter-router links for low-power, area-efficient and reliable Network-on-Chip (NoC) architectures
Abstract-- The increasing wire delay constraints in deep submicron VLSI designs have led to the emergence of scalable and modular Network-on-Chip (NoC) architectures. As the power ...
Avinash Karanth Kodi, Ashwini Sarathy, Ahmed Louri...
ASPDAC
2009
ACM
115views Hardware» more  ASPDAC 2009»
13 years 4 months ago
Frequent value compression in packet-based NoC architectures
The proliferation of Chip Multiprocessors (CMPs) has led to the integration of large on-chip caches. For scalability reasons, a large on-chip cache is often divided into smaller ba...
Ping Zhou, Bo Zhao, Yu Du, Yi Xu, Youtao Zhang, Ju...
DATE
2009
IEEE
122views Hardware» more  DATE 2009»
14 years 1 months ago
A highly resilient routing algorithm for fault-tolerant NoCs
Current trends in technology scaling foreshadow worsening transistor reliability as well as greater numbers of transistors in each system. The combination of these factors will so...
David Fick, Andrew DeOrio, Gregory K. Chen, Valeri...
GLVLSI
2009
IEEE
151views VLSI» more  GLVLSI 2009»
13 years 10 months ago
Reliability aware NoC router architecture using input channel buffer sharing
To address the increasing demand for reliability in on-chip networks, we proposed a novel Reliability Aware Virtual channel (RAVC) NoC router micro-architecture that enables both ...
Mohammad Hossein Neishaburi, Zeljko Zilic
ICS
2009
Tsinghua U.
13 years 11 months ago
A comprehensive power-performance model for NoCs with multi-flit channel buffers
Large Multi-Processor Systems-on-Chip use Networks-on-Chip with a high degree of reusability and scalability for message communication. Therefore, network infrastructure is a cruc...
Mohammad Arjomand, Hamid Sarbazi-Azad