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2000
IEEE
14 years 2 months ago
Using the DEVS Paradigm to Implement a Simulated Processor
This work is devoted to present the design and implementation of Alfa-1, a simulated computer with educational purposes. The DEVS formalism was used to attack the complexity of th...
Sergio Daicz, Alejandro Troccoli, Sergio Zlotnik, ...
CODES
2000
IEEE
14 years 2 months ago
Storage requirement estimation for data intensive applications with partially fixed execution ordering
In this paper, we propose a novel storage requirement estimation methodology for use in the early system design phases when the data transfer ordering is only partly fixed. At tha...
Per Gunnar Kjeldsberg, Francky Catthoor, Einar J. ...
DATE
2000
IEEE
97views Hardware» more  DATE 2000»
14 years 2 months ago
Layout-Oriented Synthesis of High Performance Analog Circuits
This paper presents a methodology towards synthesis of high performance analog circuits. Layout parasitics are estimated and compensated during circuit sizing. Physical layout con...
Mohamed Dessouky, Marie-Minerve Louërat, Jack...
DATE
2000
IEEE
111views Hardware» more  DATE 2000»
14 years 2 months ago
Static Timing Analysis Taking Crosstalk into Account
Capacitance coupling can have a significant impact on gate delay in today's deep submicron circuits. In this paper we present a static timing analysis tool that calculates th...
Matthias Ringe, Thomas Lindenkreuz, Erich Barke
DSN
2000
IEEE
14 years 2 months ago
From Crash Fault-Tolerance to Arbitrary-Fault Tolerance: Towards a Modular Approach
This paper presents a generic methodology to transform a protocol resilient to process crashes into one resilient to arbitrary failures in the case where processes run the same te...
Roberto Baldoni, Jean-Michel Hélary, Michel...