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ECCC
2000
158views more  ECCC 2000»
13 years 9 months ago
On the Computational Power of Winner-Take-All
This article initiates a rigorous theoretical analysis of the computational power of circuits that employ modules for computing winner-take-all. Computational models that involve ...
Wolfgang Maass
ICCAD
2010
IEEE
141views Hardware» more  ICCAD 2010»
13 years 7 months ago
Local clock skew minimization using blockage-aware mixed tree-mesh clock network
Clock network construction is one key problem in high performance VLSI design. Reducing the clock skew variation is one of the most important objectives during clock network synthe...
Linfu Xiao, Zigang Xiao, Zaichen Qian, Yan Jiang, ...
TCAD
2010
154views more  TCAD 2010»
13 years 4 months ago
Automated Design Debugging With Maximum Satisfiability
As contemporary VLSI designs grow in complexity, design debugging has rapidly established itself as one of the largest bottlenecks in the design cycle today. Automated debug soluti...
Yibin Chen, Sean Safarpour, João Marques-Si...
GLVLSI
2010
IEEE
164views VLSI» more  GLVLSI 2010»
14 years 2 months ago
Performance and energy trade-offs analysis of L2 on-chip cache architectures for embedded MPSoCs
On-chip memory organization is one of the most important aspects that can influence the overall system behavior in multiprocessor systems. Following the trend set by high-perform...
Mohamed M. Sabry, Martino Ruggiero, Pablo Garcia D...
DSD
2010
IEEE
137views Hardware» more  DSD 2010»
13 years 7 months ago
A C-to-RTL Flow as an Energy Efficient Alternative to Embedded Processors in Digital Systems
We present a high-level synthesis flow for mapping an algorithm description (in C) to a provably equivalent registertransfer level (RTL) description of hardware. This flow uses an ...
Sameer D. Sahasrabuddhe, Sreenivas Subramanian, Ku...