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ERSA
2006
105views Hardware» more  ERSA 2006»
13 years 10 months ago
A Column Arrangement Algorithm for a Coarse-grained Reconfigurable Architecture
In a coarse-grained reconfigurable architecture, the functions of resources such as Arithmetic Logic Units (ALUs) can be reconfigured. Unlike the programmability of a general purp...
Yuanqing Guo, Cornelis Hoede, Gerard J. M. Smit
CGF
2005
147views more  CGF 2005»
13 years 9 months ago
GPU Simulation and Rendering of Volumetric Effects for Computer Games and Virtual Environments
As simulation and rendering capabilities continue to increase, volumetric effects like smoke, fire or explosions will be frequently encountered in computer games and virtual envir...
Jens Krüger, Rüdiger Westermann
ICCD
2002
IEEE
152views Hardware» more  ICCD 2002»
14 years 6 months ago
Register Binding Based Power Management for High-level Synthesis of Control-Flow Intensive Behaviors
A circuit or circuit component that does not contain any spurious switching activity, i.e., activity that is not required by its specified functionality, is called perfectly power...
Lin Zhong, Jiong Luo, Yunsi Fei, Niraj K. Jha
IMSCCS
2006
IEEE
14 years 3 months ago
Verification Environment for a SCMP Architecture
The computer architecture of Single-chip multiprocessor (SCMP) is one of important research topics in developing the next-generation of computer hardware. A verification environme...
Wenbin Yao, Nianmin Yao, Shaobin Cai, Jun Ni
DATE
2002
IEEE
114views Hardware» more  DATE 2002»
14 years 2 months ago
A Video Compression Case Study on a Reconfigurable VLIW Architecture
In this paper, we investigate the benefits of a flexible, application-specific instruction set by adding a run-time Reconfigurable Functional Unit (RFU) to a VLIW processor. Preli...
Davide Rizzo, Osvaldo Colavin